Global demand for advanced packaging continues to heat up, and the market's reliance on TSMC's CoWoS production capacity has also reached its peak. According to recent foreign reports, Apple and Qualcomm clearly listed Intel's experience in packaging technologies such as EMIB and Foveros in their new job vacancies, indicating that many major manufacturers are seeking alternatives to CoWoS to cope with production bottlenecks amid the rapid growth in demand for AI and HPC chips.

Foreign media pointed out that Apple is recruiting DRAM packaging engineers, who are required to be familiar with advanced packaging technologies such as CoWoS, EMIB, SoIC and PoP. The product management director position of Qualcomm Data Center Division also lists Intel EMIB as one of the important skills.

Analysis believes that because TSMC CoWoS is currently mainly contracted by NVIDIA, AMD and large cloud customers, the scheduling flexibility of new customers is limited, causing other chip manufacturers to actively evaluate multiple packaging routes. At the same time, Intel CEO and senior management have repeatedly emphasized in the past that Foveros and EMIB have gained interest from many customers and have mass production capabilities.

According to Intel’s previous explanation, its current representative advanced packaging is divided into two major directions: 2.5D EMIB (Embedded Multi-Die Interconnect Bridge), and 3D stacked Foveros.

The former uses an embedded silicon bridge, which enables horizontal integration of multiple chips without the need for a large silicon interposer. It is a key technology used in the Intel Xeon Max and Data Center GPU Max series. The latter uses heterogeneous vertical stacking of TSVs and copper pillars, so that the top chip is not limited by the size of the base chip. It is suitable for mobile processors and customized AI accelerators, including Meteor Lake, Arrow Lake and Lunar Lake, which will all use this technology.

TSMC's CoWoS (Chip on Wafer on Substrate), which is widely concerned in the industry, is a 2.5D large silicon interposer package. It currently supports the most HBM stacks and is also the most commonly used technology for AI GPUs. Compared with Intel's two solutions, CoWoS is highly mature, has the largest production capacity, and has a wide range of HPC/GPU customers, so it is still the mainstream in the market.

To put it simply, the three major technologies are different in design and positioning:

EMIB (Intel): 2.5D small silicon bridge, suitable for horizontal integration of logic chips and HBM, with lower cost and good heat dissipation Foveros (Intel): 3D vertical stacking, can mix different processes, has high density and power saving characteristics. CoWoS (TSMC): 2.5D large-scale silicon interposer platform, which is the most popular mainstream solution for AI GPU and supports high-end HBM configurations.

Market participants pointed out that although CoWoS still occupies a dominant position in advanced packaging, as the demand for AI, data centers and customized chips accelerates, major chip companies are looking for new supply chain combinations. Apple and Qualcomm clearly named Intel technology in their job vacancies, which is seen as a signal that the industry has begun to diversify its layout. It also means that the future advanced packaging supply chain will shift from relying solely on CoWoS to gradually moving toward the possibility of a "dual supply model."

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